Minimizing Degradation of SiC Bipolar Semiconductor Devices

ABSTRACT

A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 11/022,544filed on Dec. 22, 2004. The '544 application is a continuation ofapplication Ser. No. 10/046,346 filed Oct. 26, 2001, for “MinimizingDegradation of SiC BiPolar Semiconductor Devices,” now U.S. Pat. No.6,849,874.

STATEMENT REGARDING FEDERALLY FUNDED RESEARCH AND DEVELOPMENT

This invention was developed with Government support under Governmentcontracts F33615-01-2-2108 and F33615-00-C-5403. The Government may havecertain rights in this invention.

BACKGROUND OF THE INVENTION

The present invention relates to increasing the quality and desiredproperties of semiconductor materials used in electronic devices,particularly power electronic devices. In particular, the inventionrelates to an improved process for minimizing crystal defects in siliconcarbide, and the resulting improved structures and devices.

The term “semiconductor” refers to materials whose electronic propertiesfall between the characteristics of those materials such as metals thatare referred to as conductors, and those through which almost no currentcan flow under any reasonable circumstances which are typically calledinsulators. Semiconductor materials are almost invariably solidmaterials and thus their use in electronic devices has led to the use ofthe term “solid state”, to generally describe electronic devices andcircuits that are made from semiconductors rather than from earliergenerations of technologies such as vacuum tubes.

Historically, silicon has been the dominant material used forsemiconductor purposes. Silicon is relatively easy to grow into largesingle crystals and is suitable for many electronic devices. Othermaterials such as gallium arsenide have also become widely used forvarious semiconductor devices and applications. Nevertheless, siliconand gallium arsenide based semiconductors have particular limitationsthat generally prevent them from being used to produce certain types ofdevices, or devices that can be used under certain operating conditions.For example, the respective bandgaps of silicon and gallium arsenide aretoo small to support the generation of certain wavelengths of light inthe visible or ultraviolet areas of the electromagnetic spectrum.Similarly, silicon and gallium arsenide based devices can rarely operateat temperatures above 200° C. This effectively limits their use asdevices or sensors in high temperature applications such as high powerelectric motor controllers, high temperature combustion engines, andsimilar applications.

Accordingly, silicon carbide (SiC) has emerged over the last two decadesas an appropriate candidate semiconductor material that offers a numberof advantages over both silicon and gallium arsenide. In particular,silicon carbide has a wide bandgap, a high breakdown electric field, ahigh thermal conductivity, a high saturated electron drift velocity, andis physically extremely robust. In particular, silicon carbide has anextremely high melting point and is one of the hardest known materialsin the world.

Because of its physical properties, however, silicon carbide is alsorelatively difficult to produce. Because silicon carbide can grow inmany polytypes, it is difficult to grow into large single crystals. Thehigh temperatures required to grow silicon carbide also make control ofimpurity levels (including doping) relatively difficult, and likewiseraise difficulties in the production of thin films (e.g. epitaxiallayers). Because of its hardness, the traditional steps of slicing andpolishing semiconductor wafers are more difficult with silicon carbide.Similarly, its resistance to chemical attack and impurity diffusionmakes it difficult to etch and process using conventional semiconductorfabrication techniques.

In particular, silicon carbide can form over 150 polytypes, many ofwhich are separated by relatively small thermodynamic differences. As aresult, growing single crystal substrates and high quality epitaxiallayers (“epilayers”) in silicon carbide has been, and remains, adifficult task.

Nevertheless, based on a great deal of research and discovery in thisparticular field, including that carried out by the assignee of thepresent invention, a number of advances have been made in the growth ofsilicon carbide and its fabrication into useful devices. Accordingly,commercial devices are now available that incorporate silicon carbide toproduce blue and green light emitting diodes, as a substrate for otheruseful semiconductors such as the Group III nitrides, for high-powerradio frequency (RF) and microwave applications, and for otherhigh-power, high-voltage applications.

As the success of silicon-carbide technology has increased theavailability of certain SiC-based devices, particular aspects of thosedevices have become more apparent. In particular, it has been observedthat the forward voltage (V_(f)) of some percentage of siliconcarbide-based bipolar devices tends to increase noticeably afterprolonged operation of those devices. In this regard, the term “bipolar”is used in its usual or customary sense to refer to any device in whichoperation is achieved at least partially by means of minority carrierinjection such that conduction through some region of the device isaccomplished using both electrons and holes as carriers simultaneouslyor a device in which, during forward conduction, there is at least oneforward biased p-n junction. This substantial change in forward voltagerepresents a problem that can prohibit the full exploitation of siliconcarbide-based bipolar devices in many applications. Although multipledefects may be responsible for the observed V_(f) degradation (alsocalled V_(f) drift), present research indicates that one of the causesfor the increase in forward voltage is the growth of planar defects suchas stacking faults in the silicon carbide structure under theapplication of forward current in a bipolar device. Stated differently,the passage of electric current through a silicon carbide bipolar devicetends to initiate or propagate (or both) changes in the crystalstructure. As noted above, many SiC polytypes are in close thermodynamicproximity, and solid phase transformations are quite possible. When thestacking faults progress too extensively, they tend to cause the forwardvoltage to increase in an undesirable manner that can prevent the devicefrom operating as precisely as required or desired in many applications.Other types of crystallographic defects can likewise cause degradation.The “V_(f) drift” degradation problem discussed above is a well knownand serious concern for designers of SiC power devices.

As those familiar with crystal structure and growth are well aware,perfect crystal structures are never achieved. There are a number offundamental reasons for such imperfections: all crystals vibrate andcontain a finite number of thermodynamically stable structural defects(because the crystals exist above 0 K), all are generally subject to theeffects of light or other electromagnetic radiation, all contain some(even if very few) impurities and all have an actual surface becausethey are finite in size. For these and other reasons, crystal flaws,including stacking faults, can be expected to appear even under the bestof growth circumstances.

Accordingly, there is presently a need in the art for an improvedsilicon-carbide growth technique and resulting structure that minimizesor eliminates the problem of increasing forward voltage (V_(f) drift)caused by the propagation of faults during operation, as well as amethod for forming silicon carbide-based bipolar devices that minimizesor eliminates the undesired electronic side effects of faults and theirgrowth under the application of forward current.

SUMMARY OF THE INVENTION

In a first aspect, the invention is a bipolar structure comprising asilicon carbide substrate, a voltage blocking region on the substrate,and respective p-type and n-type silicon carbide regions bounding saidvoltage blocking region. At least one of said p-type region and saidn-type region has a thickness greater than the minority carrierdiffusion length in that layer.

In another aspect, the invention is a bipolar device comprising at leastone p-type region of single crystal silicon carbide and at least onen-type region of single crystal silicon carbide, and wherein thoseportions of those stacking faults that grow under forward bias operationare segregated from at least one of the interfaces between the p-typeregion or the n-type region and the remainder of the device.

In yet another aspect, the invention is a bipolar device comprising atleast one p-type region, at least one n-type region, and at least onestacking fault, with the stacking fault being segregated from anyportion of the device that has a sufficient defect density or stressstate to support the continued growth of the stacking fault underforward bias operation of the device.

In yet another aspect, the invention is a bipolar device in siliconcarbide wherein the thickness of any stacking fault terminating layer isgreater than the minority carrier diffusion length in that layer.

The foregoing and other objects and advantages of the invention and themanner in which the same are accomplished will become clearer based onthe followed detailed description taken in conjunction with theaccompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS:

FIG. 1 is a micrograph of a prior art diode and illustrating anextensive group of stacking faults of the type addressed by the presentinvention;

FIG. 2 is a schematic perspective view of stacking faults in a prior artsemiconductor structure;

FIG. 3 is a cross-sectional schematic view of a prior art bipolar deviceand including a stacking fault;

FIG. 3A depicts the minority carrier concentration profiles during highforward current operation in a prior art bipolar diode;

FIG. 4 is cross-sectional view of a bipolar device according to thepresent invention that includes a stacking fault;

FIG. 4A depicts the minority carrier concentration profiles during highforward current operation in a bipolar diode according to the presentinvention; and

FIG. 5 is a micrograph of a diode formed according to the presentinvention and illustrating arrested lateral extension in three stackingfaults.

FIG. 6 is a schematic drawing of a bipolar junction transistor accordingto the present invention.

FIG. 7 is a schematic drawing of a field controlled thyristor accordingto the present invention.

FIG. 8 is a schematic drawing of a thyristor according to the presentinvention.

DETAILED DESCRIPTION

FIG. 1 is a photomicrograph of a prior art 1.2 mm×1.2 mm p-n diodebroadly designated at 10. The diode depicted in plan view in FIG. 1exhibits a patterned top side ohmic contact which permits visualinspection of the device during operation.

FIG. 1 illustrates an extensive group of stacking faults 11 that spansthe entire width (vertically in the orientation of FIG. 1) of thedevice. Although not visible in plan view, stacking faults 11 exist inmultiple atomic planes of device 10. This is typical of the type ofstacking fault that grows during forward operation of the device andcauses the problems referred to in the background portion of thespecification. The stacking faults 11 are formed after operation of thedevice under forward bias conditions for 30 minutes. Regions of thestacking faults are visible in FIG. 1 because they serve asrecombination centers which under some conditions produce visible lightduring forward bias operation due to electron-hole recombination at thefault. The carrier recombinations at the faults serve to decrease theefficiency and increase the forward voltage (V_(f)) of the device. FIG.2 is a schematic diagram of a semiconductor structure broadly designatedat 10A. The structure 10A can be a p-n diode, but in FIG. 2, only twoportions (a substrate and an epitaxial region) are illustrated forpurposes of clarity. In FIG. 2, a substrate is indicated at 13 and theepitaxial region of the device is indicated at 14. Typically (and asillustrated in FIGS. 3 and 4) the device 10 would also include a bufferlayer, an epitaxial n-type layer and an epitaxial p-type layer, inaddition to respective ohmic contacts.

For purposes of illustrating the present invention, stacking faultinduced V_(f) degradation will be discussed, although the invention isnot exclusively applicable to this type of defect, since other defectscan be propagated by the same mechanisms by which stacking faults arepropagated. FIG. 2 illustrates a stacking fault 15 as a triangle formedof dotted lines. Under forward operation, the stacking fault 15propagates along a (0001) plane of the material, usually in a directiongenerally indicated by arrow A (although initial nucleation and growthin other regions and directions has been observed in similar devices toa lesser extent). Thus in FIG. 2, a lower (i.e. partial) portion of asimilar stacking fault is indicated by the dotted polygon 16. Thestacking fault 16 reaches interface 12 between region 14 and substrate13 and continues to propagate in a direction generally identified byarrow B along the line 17 in the vicinity of the substrate-epilayerinterface 12. In worst-case scenarios, the growing stacking fault cangenerate additional stacking faults through the device 10 creating yetadditional problems.

In FIG. 2, the stacking fault portions 15 and 16 are shown aspropagating on an angle oblique to the top surface of the device 10A.This arises because stacking faults tend to grow along basal planes,while in many silicon carbide applications, the epitaxial layers ofdevices are grown on a slightly off-axis angle as a way of enhancing thequality of crystal growth. Thus, the particular angle of the stackingfault appears oblique in FIG. 2. U.S. Pat. Nos. 4,912,063 and 4,912,064are early examples of such off-axis growth, although the particulartechniques of these patents are offered as background rather than asspecific examples or limitations.

Typically two or more edges of the fault are pinned, often at thenucleating feature, with the remaining edges of the stacking fault onlyexpanding through the depth of the device structure where electron-holepair recombination occurs (i.e. where the minority carrier concentrationexceeds its intrinsic value during device operation). As the stackingfault extends, opportunities arise for the component dislocations toclimb to other close packed planes and generate additional stackingfaults which may propagate in the same or opposite direction. Forexample, as illustrate in FIG. 2, an “immature” stacking fault 15 hasedges 15 a, 15 b, and 15 c. Edges 15 a and 15 b are pinned at thenucleating feature N, while edge 15 c is free to extend generally indirection A. Stacking fault 16 (of which only the lower portion isillustrated, has extended all the way to interface 12 between region 14and substrate 13, where it has developed a new edge 16 d which islikewise pinned along the substrate/epitaxial interface while edge 16 cremains free to extend, generally along direction B.

The problems of planar defects such as stacking faults and the manner inwhich the invention addresses them can be understood by the additionaldisclosures of FIGS. 3 and 4. In particular, the invention can beunderstood in relation to a p-n diode, although those familiar withsilicon carbide and semiconductor devices will understand that thetechnique is applicable in many bipolar devices including, but notlimited to p-n diodes, p-i-n diodes, thyristors, insulated gate bipolartransistors (IGBTs), bipolar junction transistors (BJTs) and fieldcontrolled thyristors. FIG. 3 illustrates a p-n diode broadly designatedat 20. The diode 20 is formed on a silicon carbide substrate 21 uponwhich is an n+ type buffer 22, an n− region 23, a p-type region 24 andrespective ohmic contacts 25 and 26 to the p-type layer 24 to thesubstrate 21, respectively. A stacking fault is illustrated at 27.Together, n+ buffer 22, n− region 23 and p-type region 24 comprise avoltage blocking region or active region, with n+ buffer 22 and p-typelayer 24 comprising the boundary layers for the voltage blocking region.That is, regions 22 and 24 form the outermost regions of the activeregion of the device. It will be understood by those of skill in the artthat these regions could be grown as separate epitaxial layers by meansof an epitaxial growth method such as chemical vapor deposition (CVD),liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beamepitaxy (MBE) or other suitable epitaxial method. The respective regionsmay also be formed in one or more epitaxial layers or regions by meansof diffusion doping or implantation.

In high forward current operation of the device 20 holes are injectedfrom the p layer 24 into the n− drift region 23 as electrons areinjected from the n− drift layer 23 into the p layer 24. For theillustrated structure, the minority carrier concentration in the p+layer abruptly falls to the intrinsic level at the ohmic contact. Thisis because an ohmic contact serves as an infinite sink for electron-holepair recombination. Additionally, a significant number of minoritycarriers (holes) reach the interface 28 between the n+ buffer layer 22and the substrate 21. Given this structure, during high forward currentoperation, electron-hole pair recombinations can help to nucleate anddrive the expansion of stacking faults by glide of the dislocations(Shockley partials) that form the boundaries of the stacking faults.This recombination driven fault expansion has also been observed ingallium arsenide materials and devices.

The minority carrier concentration of device 20 is illustrated in FIG.3A. As shown in FIG. 3A, due to the relatively narrow thickness of layer24 (as compared to the minority carrier diffusion lengths in the layer),some percentage of minority carriers (in this case, electrons) injectedinto layer 34 reach the interface 29 with ohmic contact 25 where, asdescribed above, the minority carrier concentration drops abruptly tothe intrinsic level. Likewise, a percentage of minority carriers (inthis case, holes) injected into layer 22 reaches the interface 28 withsubstrate 21.

Although the inventors do not wish to be bound by any particular theory,it is presently believed that the growth of defects (especially planardefects such as stacking faults) that nucleate within the active regionis assisted by energy released during electron-hole recombinationsoccurring within the active region. Once the stacking fault propagatesto an interface or region characterized by a high density of defects orstress state, including a substrate-epilayer interface such as interface28 or an ohmic-epilayer interface such as interface 29, the continuedgrowth of the stacking fault is believed to be further assisted by thedefective region. Other interfaces besides substrate-epilayer andohmic-epilayer interfaces may have a sufficient number of defects orstress state to cause continued growth of a stacking fault.

Moreover, it is presently believed that the general dislocationdecomposition active in silicon carbide is depicted as follows usingBurgers vector notation:$ {\frac{1}{3}\langle {11\overset{\_}{2}0} \rangle}arrow{{\frac{1}{3}\langle {10\overset{\_}{1}0} \rangle} + {\frac{1}{3}\langle {01\overset{\_}{1}0} \rangle}} $

As a result of electron-hole pair recombinations, the stacking faults,such as that schematically illustrated at 27, will form and grow insilicon carbide bipolar devices such as the one illustrated in FIG. 3.As noted above, the stacking fault 27, which is present on basalplanes,is inclined to the surface of the diode because of the off-axissurface of the silicon carbide substrate wafers (usually 8 degrees offaxis towards the

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direction for the 4H polytype). Alternatively, as illustrated to someextent in FIG. 2, when viewed normal to the surface the stacking fault27 will have a generally triangular or tetragonal shape. As noted in thebackground, when the extent of faulted material becomes significant,there is a detrimental effect on the forward conduction of the device,and the forward voltage increases making the device unattractive orsimply unusable for particular applications.

In considering the design of a device in accordance with the presentinvention, a number of related factors must be considered, and to someextent balanced. For example, in a pn diode, most of the designparameters are typically developed to insure optimal blocking voltage(i.e. reverse bias) performance, and forward voltage behavior has notbeen treated as the primary concern in designing p-n diodes.Nevertheless, when blocking voltage is the desired characteristic, thefollowing progression can be followed in designing a hypothetical 5000volt (V) p-n diode structure.

First, because the n− layer will support most of the reverse voltage,the n− layer thickness is determined by applying the physical constantsto the required blocking voltage. For the 5000 V example, a minimumthickness of 45 microns (μm) is calculated based on a maximum electricfield of approximately 2.2E6 (2.2×10⁶) V/cm. Once the n− layer thicknessis set, the n− layer doping is calculated such that the n− layer will becompletely depleted under maximum design reverse voltage. For thepresent example of a 45 μm layer supporting 5000 V, a maximum doping of2.7E15 (2.7×10¹⁵ cm⁻³) is indicated.

Second, the n+ buffer is used to insure that the substrate, which isexpected to have a poorer crystal structure and thus poorer electricalproperties than the epilayer, does not support any electric field at thedesigned maximum reverse blocking voltage. Additionally, using arelatively highly doped n+ buffer is preferable to minimize seriesresistance of the diode and to minimize the necessary total epilayerthickness. Because epilayer quality generally degrades as dopingincreases above certain limits, a compromise between the need for highdoping and good crystal quality typically limits the range of acceptablen+ buffer doping to the 1E18-2E19 range, with about 2E18 being preferredfor the n+ buffer doping. Thereafter, a straightforward calculation canbe used to determine the minimum n+ buffer layer thickness for a givenstructure. Based on the example design of 5000 V reverse voltage, the n−layer being 45 μm thick and doped at 1E15, and the n+ buffer dopingbeing 2E18, a minimum n+ buffer layer thickness is 0.03 μm. The value of0.03μm serves as a lower limit and for controllable production purposes,the thickness of this layer would preferably be extended to 0.5 μm

For proper operation, the p layer must inject holes into the n− layer.Injection efficiency increases as the doping difference between theselayers increases. Typically, in such a structure, a minimal dopingdifference of about two orders of magnitude is necessary. Again, athigher doping levels, the quality of the p layer will be compromised, sofor the current example, the p doping is limited to the range of1E17-1E19, with about 1E18 being preferred. Analogously to the n+buffer, the p layer thickness is chosen so that at the full designedblocking voltage, no electric field is manifest at the top of the player. A straightforward calculation yields a minimum thickness of 0.11μm in this example, which would be increased to 0.5 μm for controllableproduction purposes.

On the very top of the p layer it is customary to use a p+ contact layerwhich will be much more highly doped than the majority of the p layer tofacilitate the formation of a low resistivity ohmic contact. This layershould be very highly doped, with 1E19 being a typical lower limit, andshould be thick enough so that damage to the crystal structure occurringduring the formation of the ohmic metal will reach not the lower dopedportion of the p layer. Typically a thickness of 0.1 μm is appropriate.

Lastly, the substrate is selected to provide a quality crystal on whichto grow the active regions of the device, and to facilitate theelectrical, thermal and mechanical connection to the device structure.Low resistivity substrates are preferable for lower series resistance,but excessively high doping introduces a number of additional problems.Thus, from a practical standpoint and with current material, thesubstrate doping is restricted to the range of 5E18-2E19. The substratethickness can be minimized to reduce the series resistance, butmechanical limitations come into play that mandate a minimum thickness,preferably at least about 125 μm after processing.

Overall, by following the reverse blocking based design procedure justdescribed, an appropriate device structure for a idealized 5 kV p-i-ncan be developed that specifies the p+ contact layer as being 0.10 μmthick and doped at 1E19; the p layer as 0.5 μm thick and doped at 1E18;the n− layer as 45 μm thick and doped at 1E15; the n+ layer as 0.5 μmthick and doped at 2E18; and a 4H n-type substrate.

In other words, in conventional design methodology, the thickness of then+ buffer layer and the p-layer in a p-n device are designed based onthe minimum acceptable thickness for reverse bias (i.e. voltageblocking) conditions. However, the conventional design methodology failsto address the problem of fault propagation (and consequent V_(f) drift)during forward bias operation. In contrast, one aspect of the presentinvention provides additional thickness design constraints based onforward bias conditions which mitigate fault propagation.

From a crystal growth and processing standpoint, the invention alsoincorporates the goal of minimizing the number of faults or otherpotential nucleation points in or near the active region of the device.Accordingly, any technique that enhances the quality of crystal growthand of the resulting substrates and epitaxial layers is generally usefulin minimizing stacking faults. In particular, it has been determined inaccordance with the present invention that continuous (rather thaninterrupted) growth of the active portions of a device—and particularlyepilayers in the active portion—tends to minimize the nucleation ofstacking faults and thus helps minimize their propagation.

A number of aspects of the invention are illustrated by the schematiccross-sectional view of FIG. 4 which illustrates in cross-sectionalfashion a p-n diode broadly designated at 30. The diode is formed of asilicon carbide substrate 31, and an n+ epitaxial layer 32 on thesubstrate 31, with the n+ layer 32 having a thickness greater than thehole diffusion length (denoted L_(p)) in the n+ layer 32. An n− layer 33of silicon carbide is on the n+ epitaxial layer and as noted previously,has a thickness and doping concentration determined by the reverseblocking voltage for the diode. A p-type epitaxial layer 34 of siliconcarbide is on the n− layer 33, and has a thickness greater than theelectron diffusion length (denoted L_(n)) in the p-type layer 34. Anohmic contact 35 is made to the p+ layer 34 and another ohmic contact 36is made to the substrate 31.

Because in one aspect the invention is based upon the relationship ofthe layer thickness to the minority carrier diffusion length, the designfactors outlined above come into play. In particular, the hole diffusionlength is determined by a number of factors including doping, that aregenerally well understood in the art. Thus—and again using the p-n diodeas the example—once the desired blocking voltage is selected, many ofthe parameters of the remaining portions of the device follow in a wellunderstood fashion. Once these parameters are met, the thickness of thep-type layer 34 and the n+ layer 32 can be extended as necessary toexceed the minority carrier diffusion length in accordance with theinvention. In the same manner, the diffusion length of the minoritycarriers can be reduced by several means including increasing themajority carrier concentration in the relevant layer. As noted elsewhereherein, the upper limit of carrier concentration is usually a practicalone, with decreasing crystal quality being the limiting factor.

It will also be understood by those of ordinary skill in this art thatthe diffusion length of a carrier (L_(p), L_(n)) is related to itslifetime according to equations (1) and (2).L _(p)=(D _(p)τ_(p))^(1/2)  (1)L _(n)=(D _(n)τ_(n))^(1/2)  (2)Thus, the invention can also be understood as providing layers withinwhich minority carrier lifetimes expire.

Expressed in yet another fashion, the invention comprises hindering thegrowth of stacking faults during operation by terminating at least oneedge of the fault in a highly doped layer. This in turn is a designfunction in that the majority carrier concentration in the highly dopedlayer directly affects the minority carrier diffusion length, with ahigher majority carrier concentration producing a shorter diffusionlength for the minority carriers. As used herein, such highly dopedlayers are preferably greater than about 5E18 cm⁻³ with the upper limitbeing determined by the desired or required crystal quality of thatlayer.

The relationship between majority carrier concentration and minoritycarrier diffusion length (or lifetime) is well-understood insemiconductor physics. These and other concepts relevant to the designand operation of semiconductor devices are generally well-understood inthis art with references such as Sze, PHYSICS OF SEMICONDUCTOR DEVICES,Second Edition (1981) John Wiley & Sons, Inc. and Sze, MODERNSEMICONDUCTOR DEVICE PHYSICS (1998) John Wiley & Sons, Inc. beingexemplary sources.

In preferred embodiments and as is common with the construction of ohmiccontacts in these types of devices, the diode can further include ap+type contact layer 37 between the p-type layer 34 and the ohmiccontact 35 for forming a better ohmic contact. Thus, the contact layer37 has a higher carrier concentration than the p-type layer 34.

In typical and preferred embodiments, the substrate 31 and the epitaxiallayers 32, 33, 34 (and potentially 37) are all of the same polytype withthe polytype generally being selected from the group consisting of the3C, 4H, 6H and 15R polytypes of silicon carbide with the 4H polytypebeing preferred for p-n diodes.

As set forth above, the prior art design parameters of the p-n diode arebased upon the desired reverse blocking voltage, and thus, using priorart design principles, the n+ epitaxial layer 32 would be only about 0.5microns thick. In contrast, in a device according to the presentinvention, n+ epitaxial layer 32 has a carrier concentration of betweenabout 1E18 and 1E19 and a thickness greater than L_(p), the diffusionlength of holes in the layer. A preferred n+ layer 32 would comprise twoseparate layers, layers 32A and 32B. Layer 32A is a 0.5 μm thick layerdoped with a carrier concentration of 2E18 cm⁻³. Layer 32 may furthercomprise layer 32B between layer 32A and the substrate 31. Layer 32B is,a boundary layer about 2 μm thick and doped with a carrier concentrationof 1E19 cm⁻³. In this embodiment, the p-type epitaxial layer 34 has athickness greater than L_(n) and has a carrier concentration of betweenabout 1E17 and 1E19. Most preferably, the p+epitaxial layer 34 is about1.5 μm thick and has a carrier concentration of about 3E18. In addition,the p+ contact layer 37 would be approximately 2 μm thick and doped1E19.

Functionally and as is generally well understood by those familiar withthis art, the p type layer 34 is selected to have a carrierconcentration of about two orders of magnitude greater than the n− layer33.

In embodiments that include the p-type contact layer 37, the contactlayer 37 preferably has a carrier concentration of at least about 1E19,but less than the amount that would result in the decrease in crystalquality that would degrade the performance of the diode. In preferredembodiments, the layer 37 typically has a thickness of about 0.1microns.

As noted above, the substrate is preferably the 4H polytype, has acarrier concentration of between about 5E18 and 2E19, and is at leastabout 125 microns thick after processing.

Summarized as an overall structure, a preferable p-n diode according tothe invention has a p+ contact layer 37 about 2.0 microns thick with acarrier concentration of about 1E19. The p-type layer is about 1.5microns thick with a carrier concentration of about 3E18. The n− layer33 is about 45 microns thick and has a carrier concentration of about1E15. The n+ layer 32 is about 2.5 microns thick and comprises a 0.5 μmthick layer with a carrier concentration of about 2E18 and a 2 μm thickboundary layer with a carrier concentration of about 1E19.

Thus, in this embodiment, the invention can be broadly considered asbeing a bipolar structure having a silicon carbide substrate with avoltage blocking region comprising respective p-type and n-type siliconcarbide epitaxial layers on the substrate and with at least one of thep-type layer and the n-type layer having a thickness greater than theminority carrier diffusion length in that layer. As those familiar withsemiconductor devices are well aware, bipolar structures can form all orportions of a number of devices, with the group consisting of p-njunction diodes, p-i-n diodes, bipolar transistors and thyristors beingthe main categories. Each of these devices has various related andderivative devices and as these are generally well understood in theart, they will not be discussed in detail herein. It will be understood,however, that the advantages in bipolar structures in silicon carbideoffered by the present invention apply to a wide variety of siliconcarbide semiconductor devices that incorporate bipolar structures.

The nature of the invention is such that it can also be understood withrespect to the characteristics of the crystal defects that are present,and minimized, using the present invention. Returning to FIG. 4, astacking fault 40 is illustrated in the cross-sectional schematic viewof the device 30. In this embodiment, the invention comprises thebipolar device 30 that has the at least one p-type layer 34 of singlecrystal silicon carbide and the at least one n-type layer 33 of singlecrystal silicon carbide. In this embodiment, those portions of thestacking fault (or faults) 40 that grow under forward operation aresegregated from at least one of the interfaces between the active regionof the device 30 and the remainder of the device 30. As used herein, theterm interface is used to indicate several structural features, all ofwhich, however, are well understood in the art. In this sense, aninterface can be a boundary between two separate epitaxial layers, or aboundary between an active and a non-active portion of a device, aboundary between an implanted and a non-implanted portion of the sameepitaxial layer, or can be broadly expressed as a portion of the devicein which a change in material system or material growth mode hasoccurred.

As an exemplary illustration rather than a limiting one, at least twointerfaces can be defined in FIG. 4. One illustrated at 41 is thephysical boundary between n+ layer 32 and the substrate 31. Another isthe boundary 42 between the ohmic contact 35 and the p+ layer 34. Acomparison of FIGS. 3 and 4 shows that in FIG. 3 (the prior art diode)the stacking fault 27 may extend all the way to the interface 29 betweenits p-type layer 24 and its ohmic contact 25. At the other end, thestacking fault extends all the way to the interface between the n+ layer22 and the substrate 21.

In contrast, FIG. 4 illustrates that the stacking fault does not extendto any of these interfaces, but instead terminates within the p-typelayer 34 and within the n+ layer 32, since the thickness of those layershas been appropriately chosen to exceed the minority carrier diffusionlength within those layers. FIG. 4A illustrates the minority carrierdistributions in device 30 under high forward current operation. Asshown in FIG. 4A, the minority carrier concentration in layers 34 and 32drops to intrinsic levels prior to reaching interface 41 or interface42. Thus, negligible electron-hole recombination occurs at interface 41and 42, and there is insufficient energy to continue propagation ofstacking fault 40 throughout the device.

In another aspect, the invention can be considered as the segregation ofthe stacking fault from those portions of the device that have asufficient defect density or stress state to support the growth of thestacking fault under forward operation of the device. Thus, because thesubstrate 31 in the device 30 in FIG. 4 is expected to have a greaterdefect density or stress state than the epitaxial layers 32, 33, and 34the invention comprises segregating the stacking faults from thesubstrate 31 and thus minimizing the chance that a stacking fault willinitiate, nucleate or grow under forward operation. In the same manner,the stacking fault 40 is segregated from the edge of the p-type layer 34that is adjacent the ohmic contact 35.

Considered in yet another aspect, the invention can be considered to bea structure in which the thickness of any stacking fault terminatinglayer is greater than the minority carrier diffusion length in thatlayer, where “stacking fault terminating layer” refers to any layer intowhich minority carriers are injected and which is bounded on a sideopposite the side on which minority carriers are injected by aninterface characterized by a high defect density or stress state. Againreturning to FIG. 4, if the stacking fault terminating layers areconsidered to be the p-type layer 34 and the n+ layer 32, the stackingfault 40 ends therein and does not extend any further because thethickness of the layer 34 and the thickness of the layer 32 have beenformed to be greater than the respective minority carrier diffusionlengths in the respective layers.

FIG. 5 is another micrograph of a diode formed according to the presentinvention and is shown in comparison to the micrograph of FIG. 1. InFIG. 5, the diode is broadly designated at 45 and again includes thegrid ohmic pattern for inspection purposes. In FIG. 5, the stackingfaults, to the extent they are visible, are illustrated at 46, 47 and48. It will be immediately noted that the expansion of the stackingfaults apparent in FIG. 5 has been arrested and as a result, thestacking faults are much less extensive than the stacking faults in FIG.1 and show the advantages of the present invention.

A diode according to the invention was fabricated as follows: A 4H SiCSi-faced substrate having an off axis orientation by an angle of 8°towards the <1120> axis was provided. All of the epilayers describedbelow were completed in a single uninterrupted growth via chemical vapordeposition (CVD). An epitaxial layer of n+ silicon carbide 2 μm thickand doped 1E19 cm⁻³ was deposited on the substrate using nitrogen as then-type dopant. Then an n+ layer 0.5 μm thick with a carrierconcentration of 2E18 cm⁻³ was deposited. Next, a 10 μm thick epitaxiallayer of n− silicon carbide having a carrier concentration of 1E16 cm⁻³was grown without a growth stop. Nitrogen was again used as an n-typedopant. Thereafter, and again without a growth stop, a p-type layer ofsilicon carbide having a carrier concentration of 3E18 cm⁻³ wasepitaxially grown to a thickness of 1.5 μm. Finally, a p+ epitaxiallayer having a thickness of 2 μm was grown on the p-type layer. The p+layer had a carrier concentration of 1E19 cm⁻³. Ohmic contacts were thenformed on the top an bottom surfaces of the device.

After fabrication and operation for 30 minutes, the growth of stackingfaults 46, 47 and 48 was arrested such that they did not continue topropagate throughout the width of the diode. The present invention maybe employed in bipolar devices other than pn diodes. For example, asillustrated in FIGS. 6-8, the invention may be employed in other typesof bipolar devices including, without limitation, bipolar junctiontransistors and thyristors.

An embodiment of the invention in a bipolar junction transistor (BJT) isillustrated in FIG. 6. BLT 600 comprises an n-type SiC substrate 602, ann+ buffer 604, an n− voltage blocking layer 606, a p-type base region608 and an n-type emitter region 614. Ohmic contacts are deposited toform collector contact 620, base contacts 612 and emitter contact 616.In order to arrest the propagation of planar defects, n+ buffer layer604 and n+ emitter region 614 are each made thicker than the minoritycarrier (hole) diffusion length in those layers, to prevent minoritycarriers from diffusing to the interface between buffer layer 604 andsubstrate 602, and the interface between emitter region 614 and ohmiccontact 616, respectively.

A further embodiment of the invention is illustrated in FIG. 7, whichshows a buried gate field controlled thyristor (FCT) 700. FCT 700comprises an n-type SiC substrate 702, an n+ buffer layer 704, a p−drift region 706 in which an n+ gate 710 is buried, and a p+ anode layer708. Ohmic contacts 712 and 720 form anode and cathode contacts,respectively. In order to arrest the propagation of planar defects, n+buffer layer 704 and p+ anode layer 708 are each made thicker than theminority carrier diffusion lengths in those layers, to prevent minoritycarriers from diffusing to the interface between buffer layer 704 andsubstrate 702, and the interface between p+ anode layer 708 and ohmiccontact 712, respectively.

Yet another embodiment of the invention in a thyristor structure isillustrated in FIG. 8, in which thyristor structure 800 comprises a SiCsubstrate 802, an n+ buffer layer 804, a p− voltage blocking layer 806,and an n-type layer 808. A plurality of p+ anode regions 810 are formedon an upper surface of n-type layer 808. Ohmic contacts are deposited toform anode contacts 812, gate contacts 814 and cathode contact 820. Inorder to arrest the propagation of planar defects, n+ buffer layer 804and p+ layer 810 are each made thicker than the minority carrierdiffusion lengths in those layers, to prevent minority carriers fromdiffusing to the interface between buffer layer 804 and substrate 802,and the interface between p+ layer 810 and anode contacts 812,respectively.

Those having skill in the art will recognize that the invention may beembodied in many different types of bipolar device structures.Accordingly, the invention is not limited to the particular structuresillustrated herein.

In the drawings and specification there has been set forth a preferredembodiment of the invention, and although specific terms have beenemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being defined inthe claims.

1. A method of forming a bipolar semiconductor device that minimizes thepropagation of stacking faults through the device, the methodcomprising: growing a first stacking fault terminating layer of siliconcarbide of a first conductivity type on a silicon carbide substrate;growing a silicon carbide voltage blocking drift region on the firststacking fault terminating layer; growing a second stacking faultterminating layer of silicon carbide on the drift region, wherein thesecond stacking fault terminating layer has the opposite conductivitytype as the first stacking fault terminating layer; doping at least aportion of each stacking fault terminating layer to a higher carrierconcentration than that of the drift region to reduce the minoritycarrier lifetime in that portion of each stacking fault terminatinglayer and to arrest the propagation of stacking faults through thedevice.
 2. A method according to claim 1, comprising doping the firststacking fault terminating layer to a carrier concentration in the rangeof 1×10¹⁸ to 2×10¹⁹ cm⁻³.
 3. A method according to claim 1, comprisingdoping the second stacking fault terminating layer to a concentrationthat is about two orders of magnitude greater than the dopingconcentration of the drift region.
 4. A method according to claim 1,comprising growing the first stacking fault terminating layer in twostages, wherein the first stage of growth forms the lower portion of thefirst stacking fault terminating layer with a first dopingconcentration, and the second stage of growth forms the upper portion ofthe first stacking fault terminating layer at a second dopingconcentration that is lower than the first doping concentration.
 5. Amethod according to claim 4, comprising doping the lower portion of thefirst stacking fault terminating layer to an n-type doping concentrationof about 1×10¹⁹ cm⁻³.
 6. A method according to claim 4, comprisingdoping the upper portion of the first stacking fault terminating layerto an n-type doping concentration of about 2×10¹⁸ cm⁻³.
 7. A methodaccording to claim 1, comprising doping the second stacking faultterminating layer to a p-type doping concentration of about 3×10¹⁸ cm⁻³.8. A method according to claim 1, comprising growing a p+ type contactepitaxial layer on the second stacking fault terminating layer anddoping the contact layer to a carrier concentration of about 1×10¹⁹cm⁻³.
 9. A method of forming a bipolar semiconductor device thatminimizes the propagation of stacking faults through the device, themethod comprising: growing a first stacking fault terminating layer of afirst conductivity type to support the active region of the device;growing the active region on the first stacking fault terminating layer;growing a second stacking fault terminating layer on the active region,wherein the second stacking fault terminating layer has the oppositeconductivity type as the first stacking fault terminating layer; whereinat least one of the first and second terminating layers are grown to athickness greater than the minority carrier diffusion length in thatlayer to arrest the propagation of stacking faults through the device.10. A method according to claim 9, further comprising the step of dopingat least a portion of each stacking fault terminating layer to a highercarrier concentration than that of the drift region to reduce theminority carrier lifetime in that portion of each stacking faultterminating layer.
 11. A method according to claim 9, wherein the firststacking fault terminating layer is grown to a thickness of about 2.5microns.
 12. A method according to claim 9, comprising doping the firststacking fault terminating layer to a carrier concentration in the rangeof 1×10¹⁸ to 2×10¹⁹ cm⁻³.
 13. A method according to claim 9, comprisingdoping the second stacking fault terminating layer to a concentrationthat is about two orders of magnitude greater than the dopingconcentration of the active region.
 14. A method according to claim 9,comprising growing the first stacking fault terminating layer in twostages, wherein the first stage of growth forms the lower portion of thefirst stacking fault terminating layer with a first dopingconcentration, and the second stage of growth forms the upper portion ofthe first stacking fault terminating layer at a second dopingconcentration that is lower than the first doping concentration.
 15. Amethod according to claim 14, comprising doping the lower portion of thefirst stacking fault terminating layer to an n-type doping concentrationof about 1×10¹⁹ cm⁻³.
 16. A method according to claim 15, comprisingdoping the upper portion of the first stacking fault terminating layerto an n-type doping concentration of about 2×10¹⁸ cm⁻³.
 17. A methodaccording to claim 9, comprising doping the second stacking faultterminating layer to a p-type doping concentration of about 3×10¹⁸ cm⁻³.18. A method according to claim 9, comprising growing the secondstacking fault terminating layer to a thickness of about 1.5 microns.19. A method according to claim 9, comprising growing a p+ type contactepitaxial layer on the second stacking fault terminating layer anddoping the contact layer to a carrier concentration of about 1×10¹⁹cm⁻³.
 20. A method according to claim 9, wherein the layers are grownvia continuous chemical vapor deposition.